This invention relates to signal integration devices, and more particularly to a digital delay line integrator.
Developments in integrated circuit (IC) technology have made possible compact, yet sophisticated, signal integration techniques in airborne search radars. Radar integration is normally noncoherent and performed at video frequencies, rather than coherent as it would be if it were performed at IF. This is because a mere half wavelength change at RF in the range between radar and target results in 180.degree. phase change at IF. With noncoherent integration, thermal noise adds up as fast as target and clutter signals. The improved visibility of the return echo signals results from the fact that, over time, noise fluctuations average out so that the integrated noise signals become a relatively smooth baseline under the return echoes. Even though integration is implemented physically as a simple addition process, it may be considered an averaging process because the overall system gain is arbitrarily chosen to give a convenient output level.
Integration may be performed with continuous storage devices such as CRT screens and analog delay lines, or discrete storage devices such as capacitors and digital circuits. The signal level in a discrete storage device represents in some fashion the returns from some finite range interval. Even though the time interval that is sampled to provide the signal to store in a discrete storage device may be chosen arbitrarily small, the range interval represented cannot be smaller than a resolution cell. However, the circuit designer thinks in terms of time intervals rather than range intervals, so to him a resolution cell is a time interval. The range resolution, or resolution cell, of a radar is normally taken to be c.tau./2, where c is the speed of light and .tau. is the transmitted pulse duration.
Since a separate storage device must be used for each resolution cell, many storage devices must be used to cover a large range interval if discrete storage devices are used. For this reason, analog delay lines have been proposed as a simpler means of integrating the returns from many resolution cells simultaneously. The output of the delay line would be added to the incoming video signals and the sum would be fed into the input of the delay line. If the delay line were the same length (in units of time) as the pulse repetition interval (PRI) of the transmitter, then incoming returns from any particular range would be added to previous returns from the same range, and a satisfactory integration process would result. However, it has proved difficult to fabricate analog delay lines with the required combination of delay, bandwidth, and small size. Recently, IC technology has advanced to the point that digital delay lines now may be constructed which are suitable for these purposes by combining large numbers of storage devices in a single IC. Just a few such ICs can be used to make a digital delay line.
A digital delay line may be constructed by connecting a separate shift register IC to each of the output terminals of an analog to digital (A/D) converter. An A/D converter has one analog input, as many parallel digital output terminals as there are bits of resolution in the conversion process, and a clock input. When a clock pulse arrives, a digital word, or binary number, appears at the output terminals. This digital word represents the voltage level at the analog input just before the arrival of the clock pulse. This digital output is held until the next clock pulse.
Digital delay lines are constructed with an A/D converter and as many shift registers as there are bits of resolution, and therefore output terminals, in the A/D converter. A digital delay line (DDL) integrator in a radar does not require the use of a fixed PRI the way an analog delay line does, since the signals remain fixed in the delay line when the digital clock signal is withheld.
The simplest and least expensive digital delay line integrator is the periodic dumping integrator. It integrates for a fixed number of pulses, then dumps the stored data and starts integrating again. The partial feedback integrator differs from the periodic dumping integrator in that it is continuously dumping. The serial delay line integrator does not employ feedback, but sends the signals serially through successive delay lines in series with each other. The number of delay lines used is one less than the number of pulses to be integrated. The signal going into each of the delay lines, and the one coming out of the last delay line, are added to form the output signal.
The disadvantage of the periodic dumping integrator is the limited amount of data which it can integrate. The partial feedback integrator is a leaky integrator, i.e., for high efficiency the decay time is long, but for short decay time the efficiency is low. The serial delay line integrator processes more data, but the number of delay lines required is prohibitive.